Thorough understanding of FPGA design process including requirements generation, preliminary design, peer reviews, detailed design, test plan generation, and integration and test.
Experience with high speed memory interfaces (DDRx)
Experience with high speed serial protocols (PCIe, JESD204B)
Experience with SoC designs incorporating ARM series embedded processors (Xilinx Zynq/Altera Stratix SoC)
Solid understanding of digital logic design concepts and how VHDL code translates into FPGA Fabric; detailed understanding of the architectural elements within modern Xilinx UltraScale and/or Altera Arria & Stratix 10 FPGAs.
High Level Design using C/C++ and/or OpenCL
Solid understanding of static timing analysis and the process by which timing closure is achieved in a design
Must have a thorough understanding of the Vivado or Quartus tool suite used to generate FPGA designs
Experience using Mentor Questa/ModelSim Simulator, Revision Control (SVN, MKS), Scripting Languages (TCL, Python, Perl)
Experience integrating with HW/software and supporting the complete testing and qualification of the deliverable system
Must be able to work independently with minimum supervision
BS Degree in electrical/computer engineering and 6+ years or related experience
Ability to obtain DoD secret security clearance
Basic knowledge of computer network protocols
Implementation of Signal Processing related designs (Radar, Comm) in FPGAs
Must be able to work with the System Engineer and flow system specifications down to the FW specifications
Ability to work in a team environment and negotiate solutions with Hardware / Software Engineering and Systems Engineering
Strong technical background to lead a team of designers to architect the firmware and in generating a Firmware design solution
This position requires the candidate to possess or have the ability to obtain a DoD secret security clearance. In order to obtain a clearance you need to be a US Citizen and show proof of citizenship.